Since their introduction in 1980, Field Programmable Logic Devices (FPLD) have been an integral component for digital circuit implementation. This modern variant for realizing digital circuitry offers great advantages relative to conventional VLSI designs in terms of production costs, short product development for the market (fast market maturity), and favorable system modification.
These FPLDs also exhibit complex programmable wiring in addition to programmable logic. Therefore, the realization of multi-stage logic is possible. Programmable wiring is typically realized in a corresponding switch matrix, which, however, limits the complexity of the wiring. Recent years, however, have shown especially strong development of applications for Field Programmable Gate Arrays (FPGA) in technological fields associated with FPLDs.
Because FPGAs allow arbitrarily distributed combinatorial logic circuits to be linked together with complex patterns using sequential circuit parts, this method can produce universal, scaleable circuits. Therefore, it is especially advantageous to design and manufacture user-programmable circuits in this technological field. This can be seen especially clearly in the state of the art in the tendency of frequent development of microcontrollers and procedure controllers, etc., as FPGAs.
A distinct number of large manufacturers (e.g., ACTEL, XILINX) have introduced their FPGAs, which can be programmed by the user, as de-facto standards to the market. For these available circuit types, one can define basic structures, for which the FPGAs consist of an array of complex logic blocks. Here, not only the configurations of logic blocks themselves, but also the connections between the logic blocks, can be programmed.
Thus, in the state of the art, the combinatorial circuit part of a common configurable logic block (CLB) consists of look-up tables (LUT), which are preferably realized by static RAM. Arbitrary combinatorial functions, which are represented by truth tables, are converted into these look-up tables. For these truth tables, one also speaks of function tables, which can be realized by matrix memories and expanded, e.g., by multiplexers, or just by the memories alone.
The sequential functions of the configurable logic blocks (CLB) are executed by sequential CLB control logic, whose memory elements represent D-FFs. Because the individual CLBs are usually arranged like a grid in FPGAs, the wiring of these CLBs is also grid-like. The programmable wiring of the CLBs mentioned above is realized by switches at the interfaces, e.g., with so-called pass transistors.
The FPLDs in general and the FPGAs in particular are preferably used for applications in communications technology, in process control technology, for industrial device controllers, etc., because these areas of application are very computation-intensive. On one hand, FPGAs have also gained widespread importance for implementing signal processes and algorithms, because here, these can be executed very effectively as parallel processes. On the other hand, the transformation of such parallel calculations into hardware realized by FPGAs also means that complex computational and control processes, as represented, e.g., by conditional branches, experience a similarly complex realization in their CLBs.
For this realization of CLBs, it is obvious that for certain applied cell architectures, which are characterized by frequent applications of standard cell gates (fine-grain), many wiring elements are necessary and/or for frequent use of complex logic (coarse-grain), logic also frequently remains unused. To realize complex user circuits using this FPGA technology, these difficult-to-balance portions of unused logic elements and/or additional wiring elements have a counter tendency to lower the efficiency, which leads to a somewhat higher use of area for the circuit, e.g., relative to comparable VLSI/CPLD realizations.